Partitioned Cache Architecture as a Side-Channel Defence Mechanism
نویسنده
چکیده
Recent research has produced a number of viable side-channel attack methods based on the data-dependant behaviour of microprocessor cache memory. Most proposed defence mechanisms are software based and mainly act to increase the attackers workload rather than obviate the attack entirely. In this paper we investigate the use of a con gurable cache architecture to provide hardware assisted defence. By exposing the cache to the processor and allowing it to be dynamically con gured to match the needs of a given application, we provide opportunity for higher performance as well as security.
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عنوان ژورنال:
- IACR Cryptology ePrint Archive
دوره 2005 شماره
صفحات -
تاریخ انتشار 2005